Wafer Acceptance Test Engineer

Responsibilities

. To develop and maintain foundry PCM test pattern layout and description.

. To develop and run SVRF/Tcl scripts to generate layout pattern according to device truth table and design support manual

. To collaborate with design,integration lithography and MES team to facilitate mask making process

. To troubleshoot test pattern layout issue and optimize it

. To setup and calibrate TCAD deck file to provide device tuning and process optimization condition

. To maintain EDA software and user accounts

. Knowledge of Linux OS will be an adding advantage

. Experience of using EDA software Cadence layout, Synopsys Laker ,TCAD and Semens Calibre will be an adding advantage

Requirements

. Candidate must possess at least a Bachelor's Degree, Engineering(Electrical/Electronic) or equivalent.

. Semiconductor physics knowledge is must-be

. At least 2 years working experience in semiconductor foundry industry